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ASIC Design and Synthesis

Name: ASIC Design and Synthesis
Brand: Springer Verlag, Singapore
SKU: 38574120
Price: 140.01 EUR
Availability: InStock
Author: Vaibbhav Taraate
ISBN: 9789813346444

RTL Design Using Verilog

Vaibbhav Taraate

Language

English

Book Paperback

Libristo code: 38574120

Publishers Springer Verlag, Singapore, January 2022

This book describes simple to complex ASIC design practical scenarios using Verilog. It builds a s... Full description

Libristo code: 38574120

341 b

140.01 €

273.84 лв

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This book describes simple to complex ASIC design practical scenarios using Verilog. It builds a story from the basic fundamentals of ASIC designs to advanced RTL design concepts using Verilog. Looking at current trends of miniaturization, the contents provide practical information on the issues in ASIC design and synthesis using Synopsys DC and their solution. The book explains how to write efficient RTL using Verilog and how to improve design performance. It also covers architecture design strategies, multiple clock domain designs, low-power design techniques, DFT, pre-layout STA and the overall ASIC design flow with case studies. The contents of this book will be useful to practicing hardware engineers, students, and hobbyists looking to learn about ASIC design and synthesis.